Since the original analytical and experimental work on charge-coupled devices (CCDs) in semiconductor technology, significant effort has been expended toward improving the devices themselves and applying the devices to large scale systems. Thus CCDs have for some time been used in analog applications, but more recently have successfully been adapted to digital memories and digital signal processors. Particular advantages arise for a number of system configurations, because of the extremely low power requirements and high density properties of the CCD in comparison to other forms of large scale integration.
The CCD comprises a capacitive semiconductor device having a potential well which can not only store an incremental packet of charge but which can transfer that charge packet to an adjacent similar device. Thus, in a digital system, the presence or absence of a substantially full charge in a potential well conveniently represents one or the other binary state, and data storage and transfer operations are readily implemented. CCDs are particularly advantageous for systems in which sequential processing and storage of long chains of binary values are important, as in many real time processing and analysis systems. However, there are transfer inefficiencies at each storage site, so that a continuously diminishing charge packet would be transferred if the charge packet were not restored or regenerated periodically to its full level. The CCD is essentially a metal-oxide semiconductor capacitor that is biased by an electrical field to create a substrate region that acts as a localized potential minimum for mobile carriers in a charge packet. Transfer of the mobile charge carriers to an adjacent storage site is effected by proper interrelationships between the voltages on adjacent electrodes, so that moving potential wells are established which ultimately carry the charge packets to a device at which their presence or absence is sensed. Although the present description relates to a particular example of a system using negative bias for the potential wells under the electrodes, it will be appreciated by those skilled in the art that either polarity may be used in accordance with whatever substrate is selected. Similarly, it will be recognized that practice of the invention is not dependent upon use of any particular fabrication technique, such as the use of buried channels as opposed to surface channels.
The transfer inefficiencies result from unavoidable imperfections in semiconductor and device manufacture, and a number of workers in the art have confronted the problem in different ways. The common expedient is to insert active elements in the system, but this not only substantially increases the power requirements but requires that a substantial amount of area be devoted to the regeneration function. It is of course desirable that the signal-to-noise ratio be adequately high to correspond to the very high reliability demanded of digital systems. Thus, a charge packet can only be allowed to diminish to that level at which it may reliably be regenerated without more than a negligible chance of an error occurring, as determined by system reliability requirements. Obviously, however, the lower the charge packet can be relative to the 100% level, without affecting reliability, the fewer the number of regenerators that need be used and the greater the packing density of the CCD array. Similarly, the digital system must incorporate a great many logical and arithmetic gates, and its packing density can be substantially increased if automatic regeneration functions can be incorporated directly into these gates, or at least a substantial proportion of them as needed.
The prior art as to regenerator devices is exemplified by U.S. Pat. Nos. 4,048,519, 4,047,051 and 3,986,059. The prior art on logic devices is exemplified by U.S. Pat. No. 3,777,186. As pointed out in a patent application entitled "Logic Gate Utilizing Charge Transfer Deviced", Ser. No. 724,140, filed Sept. 17, 1976 and assigned to the assignee of the present application, the circuit of U.S. Pat. No. 3,777,186 is subjected in practice to a race condition and the erroneous transfer of charge which substantially diminishes the reliability of the circuit. In the aforementioned application, transfer gates and control gates are employed in conjunction with what is termed a charge sensing amplifier. The charge sensing amplifier incorporates a master gate and an interrelated slave gate to control output transfer of charge packets whose presence or absence indicates the appropriate binary value. Although arithmetic and logic functions are provided, charge regeneration must be effected separately.